double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 1 of 6 double pulse test board ? features compatible ? 1200 v, 100 a testing ? low series inductance design ? wide, 6 oz. copper current traces ? multiple dut and fwd connections for long life ? compatible with genesic gate drive mounting ? low resistance and induct ance gate drive connection ? ? to-257 packaged high temperature sjts ? to-258 packaged high temperature sjts ? to-46 packaged high temperature sjts electrical characteristics parameter symbol conditions value unit notes test voltage maximum v ds, max 1200 v drain current maximum i d, max 100 a capacitor bank c bank 5.0 f parasitic inductance l s hv = 800 v, i d = 6 a 62.5 nh maximum stored energy e max hv = 1200 v 3.6 j overview the genesic double pulse test board is designed for performing double pulse switching tests on genesic sic junction tr ansistors (sjt) as well as other three terminal switchi ng transistors. it is designed u sing low esl capacitors and pcb traces to feature a low parasitic series ind uctance (l s ) current path. this is necessary to record data which is most representative of the device under test (dut) and minimize test ing circuit distortions. the board is capabl e of reaching a maximum of 1200 v and 100 a for high power device testing. an external loa d inductor, dut, and free-wheeling diode (fwd) are soldered to the board wi thout sockets for the lowest possible contact resistance and inductan ce. genesic pin compatible gate drive boards may be mounted directl y on to the test board for ease of use while also having a short, lo w inductance path to the dut gate pin connection. figure 2: genesic semiconductor switching test board schematic v ds, max = 1200 v i d, max = 100 a figure 1: genesic semi double pulse test board
double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 2 of 6 figure 3: switching test board with labeling mhv voltage connection high voltage for testing up to 1200 v is supplied to the test b oard through a mhv coaxial connection. voltage may be generated through a high voltage power supply of choice. capacitor bank the capacitor bank is comprised of 20, 1 f, 630 v capacitors t o store up to 3.6 j of energy to supply to the dut. the bank in cludes 10 low effective series inductance (esl ) surface mount ceramic capacit ors to allow dut drain currents to rise and fall with minimal c ircuit interference. thick 6 oz. copper traces on the te st board also minimize this parasitic inductance and connect t he capacitor bank to the test circuit. voltage balancing network a voltage balancing network of two 1 m?, 2 w smd resistors is u sed to ensure an equal potential is across the series connected capacitors on the test board along with two blocking rectifiers to protect ag ainst extreme overvoltage of the energy storage capacitors. external load inductor connection a load inductor (not provided) is soldered directed to the hv a nd drain nodes upon the connecti on pads provided. care should b e taken to ensure the voltage rating of the inductor is not exceeded. also , if the chosen inductor value is too large the capacitor bank may drain before the inductor is fully charged to the desired test current i d level. an inductance of l load 1.0 mh is suggested. device under test (dut) and free wheeling diode (fwd) the dut and fwd are to be soldered into the connection terminal s with minimal lead extending from the board, extra leads exten ding through the test board should be trimmed from the package to reduce ele ctrical noise which may distort measurement during ultra-fast, high-voltage switching which sjt devices are capable of. devices may be conn ected to isolated hotplates while connected to the test board f or high- temperature testing as desired. it is also recommended to probe any device voltages (i.e. v gs , v ds ) as close as possible to the device for accurate measurement and minimal testing induced voltage and current rin ging. gate drive conn. drain current sensor conn. dut 5 f capacitor bank mhv voltage conn. voltage balancing + external load inductor connection C fwd
double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 3 of 6 drain current sensor connection a low inductance measurement of the dut drain current can be ma de utilizing the drain current sensor connection along with the use of a pearson electronics current mon itor (not provided) of the shape j. the connection can best be made utilizing a wide metallic conductor extending from the gnd node partially encasing the current moni tor with a wide conductor extending through the current monitor eye-hole and connecting to the source node beneath. these two nodes, source and gnd, must be connected for the test board to operate proper ly and when used in this configuration the drain current passed throug h a current monitor for data recording while adding minimal par asitic inductance. if the drain current is not being sensed at the drain current s ensor connection in some fashion, as described here or otherwis e, the two nodes must be shorted together using a wide jumper cable. figure 4: drain current sensor connection with pearson current monitor installed using a low inductance current path. gate drive connection the gate drive connection may be used to connect a genesic gate drive board to the test board and dut. it is designed to recei ve the gate drive board voltage inputs from an external supply as well as t he digital gate control signal and pass them through the test b oard to the gate drive board inputs through a 6 pin, in-line header connection. the output gate connection of the gate drive board is directly fed into the test board gate node through a 3 pin header and is passed with a low parasitic inductance connection to the dut gate pin along with a similar source connection return. the use of the gate drive connection is opti onal and dut gate driving is ful ly customizable to the users s pecifications and preferences. the connection of any gate drive topology may be m ade to the gate drive connection or directly to the dut. figure 5: genesic gate drive board connected to the test board s gate drive connection
double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 4 of 6 figure 6: sjt 800v switching turn on waveform figure 7: sjt 800v switching turn off waveform
double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 5 of 6 top side copper metallization bottom side coppe r metallization figure 8: test boards top and bottom copper pours.
double pulse test board GA100SBJT12-FR4 sept 2014 http://www.genesicsemi.com/ pg 6 of 6 revision history date revision comments supersedes 2014/09/15 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. res erves right to make changes to t he product specifications and dat a in this document without not ice. genesic disclaims all and any warranty and liability arising ou t of use or application of any product. no license, express or implied to any intellectual property rights is granted by this document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life-saving, medical, aircraft navigation, communication, air traffic control and weapons syst ems, nor in applications where their failure may result in deat h, personal injury and/or property damage.
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